Your present location:Home >> Technical schemeNew design method and function

A leading global Xilinx Inc All Programmable technology and devices (Xilinx, Inc.(NASDAQ:XLNX)) Vivado Design Suite version 2013.3, provides a new UltraFastTMdesign method, enhanced the plug and play IP configuration, integration andverification, and partial reconfiguration (Partial Reconfiguration) function. AllProgrammable device Vivado ® design suite and Xilinx are collaborative optimization,is the industry's only programmable SoC enhanced design suite, can solve the problem of system level and implementation of integrated productivity bottlenecks.

Automatic support for the latest UltraFast design method

In order to speed up the design process, the accurate prediction of design schedule,Vivado Design Suite version 2013.3 includes automatic function of UltraFast designelements, which provide rules for the design of examination (DRC), which can guide the Engineer in the entire design cycle step by step to carry out design work, the hardware description language (HDL) and constraint template, you can achieve thebest the results of quality.

Plug and play IP configuration, integration and verification function enhanced

Xilinx introduced in 2012 a plug and play IP, IP integrated with IP-XACT, IEEEaccelerated P1735 encryption and AMBA ® AXI4 protocol and other industry standards. Earlier this year Vivado design suite provides the industry's first plug and play IP integrated design environment of Vivado IP integration (Vivado IPI), broke through the limitations of RTL design productivity.

Vivado Design Suite version 2013.3 by enhanced IP integrated function, significant progress has been made in terms of ease of use, and to provide more than 230LogiCORE ™ and SmartCORE ™ IP nucleus. After the upgrade, the system level design and Xilinx IP collaborative optimization. For example, designers can now in the whole process of design and the Ethernet MAC or PCIe ® connection function IP clock shared resources. If you want to upgrade IP, transceiver debugging port can easily access the IP from the top. Designers can not only through the new function using Vivado logic analyzer at run time for AXI system fully read / write access, and they can also be used for hardware debugging with the trigger function of advanced, capture the complex events detection and.

The integration of Vivado Design Suite 2013.3 package also further simplified IP andrevision control system, and can automatically run validation process with CadenceIncisive Enterprise simulator and VCS simulator Synopsys.

Partial reconfiguration

Vivado Design Suite version 2013.3 supports partial reconfiguration. The ISE designkit is also provided with the function of many customers, has been successfully adopted. Partial reconfiguration can be dynamically change function, thus improving device resource utilization. In addition, partial reconfiguration can reduce the power consumption, but also under the condition of no stop system field upgrade.

Firmware engineering manager of Tendium company Stephen Frey said: "PartialReconfiguration Using Xilinx Vivado Design Suite for 7 series devices are available,Trendium is to meet our PCI Express ® requirements, successfully developed asystem on chip architecture. With the aid of the partial reconfiguration technology, wecan not disturb the PCI Express link the case for our network access agent platform replacement protocol analysis module, so as to improve the effective utilization rate ofXilinx devices. The method can also be used a new module to update existinghardware, providing enhanced features for future products."

@Copyright 2014 Avnet Electronics Marketing Asia
AvnetInc | Site map | Terms | Legal Disclaimer | Privacy treaty